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Measuring Signal Eye Diagrams of Transmitted Data
1.
Connect a 50- ? SMA cable between the TX_P0 through TX_P5
connectors on the board (depending on the channel for which the
eye-diagram needs to be measured) and Ch1 on the TDS8000
sampling module.
1
The TX_P5 channel has a 40 inch trace between the FPGA
serial data output pin and the SMA connector.
2.
Connect an equal length 50- ? SMA cable between the TX_N0 and
TX_N5 connectors on the board and Ch2 on the TDS8000 sampling
module.
1
The TX_N5 channel has a 40 inch trace between the FPGA
serial data output pin and the SMA connector.
3.
4.
1
Connect a 50- ? SMA cable between the clock trigger output (J3 or J4
depending on which clock is specified as the design’s refclk ) and
the direct trigger input on the TDS8000 front panel.
Customize the TDS8000 to measure the eye diagram on differential
data streams. You can do this by using the math utility provided on
the sampling oscilloscope. Setting up the math utility to measure
eye diagrams on Ch1-Ch2 effectively gives a differential eye
measurement (See Figure 2–6 ).
Use the DC block for high-speed signals going into the
oscilloscope, e.g., TX_P0 , and TX_N0 . For the trigger clock
output from the Stratix II GX transceiver signal integrity board,
use the DC block. Also use the attenuator depending on the
allowable input voltage range of the oscilloscope.
2–18 Getting Started User Guide
Altera Corporation
Transceiver Signal Integrity Development Kit, Stratix II GX Edition
June 2006
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